RE: Misc 34

["Wayne Morellini" <waynemm@xxxxxxxxxxx>]

I just realised that this got unsent.

From: <eugene.leitl@lrz.uni-muenchen.de>

   (((Here's some marketing crap I keep being spammed with from Tao
     Group. I hope they all die of gangrena, and smell horribly)))

It would be if it wasn't so true (even QNX uses their Java technology).  
Lets hope that they can pull it off (to market).  I welcome it, it can give 
Microsoft a serious run for it's money.    It is a look at the way OS's 
should operate, for users.  I aimed to do a simpler misc system with simular 
objectives years ago.

   From: "Bill Blunn" <bill@tao-group.com>

   High performance, memory efficient solution for running Java(TM)
   technology based media content across consumer digital appliances.


Jeff wrote:

 > 8u for a few more before Mosis shut down the .8u
 > fab
 > line last year.  He has been talking about the jump to .5u or two jumps 
to
 > .35u for while.
There must be other processes that this could be applied to that don't get 
outdated (I mean the
logical design, guys working on programable silicon please take note).  I 
have heard of a number
of macro processes based on electrical ink (yes, use your ink jet) maybe 
even photocopying, and
plastic paper.  These things are serious business and quiet cheap to use.  A 
misc core would get
really good results out of this process (admittedly with a dram chip in the 
corner).  Another
process was plastic you could form circuits on by shining light on them 
(around 1 Micron lines).
There is a process comparable to .35 micron that you stamp the circuit on 
(talk about cheap
prototyping).  There are viable alternatives out there that aren't normally 
found.

>.15u process stuff is cool.  It would fun to do multigigahertz stuff.
(With embedded dram?).

It's a shame that we can't get a monthly report on the Misc group about 
what's happening and
the other issues we are discussing (unfortunately only Jeff and Chuck have 
access to this
information, and are already doing enough).

From: Alan Tutt <alant@ionline.com>
>The viewpoint that I am working on here is not a cache-type memory, as
>some readers have seemed to indicate in their responses, but as an
>addressable memory block that may be reserved for frequently used code
>or data.
...........
>The only off-chip memory accesses would be for additional
>data that could be loaded a full memory page at a time, taking advantage
>of page-mode access.  Wouldn't this be the most efficient method of
>utilizing memory space?

IA, IA!  It is a good compromise.

From: Jeff Fox <Jfox@a-p-i.com>

>It is fast.  In production it is relatively cheap.  I have mentioned
>prototyping issue of paying $100 per word.  But F21c did have some on-

Jeff, is it possible to leave the memory prototyping until the rest of the 
chip is finished, saving
this expense till the last prototypes?  Will paged dram be available at less 
than embedded ram
prices in a few years?

Wayne

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