F21 Network Coprocessor
- To: misc
- Subject: F21 Network Coprocessor
- From: Dave Lowry <lowry@xxxxxxxxxxxxxxxxx>
- Date: Wed, 6 Sep 2000 18:01:07 -0500 (CDT)
Thanks, Jeff, for your reply! But, I'm still confused :-(
The model I have in my head resembles regular asynchronous serial
reception. That is, after the start bit edge, we count 1/2 bit time
to get into the center of the bit and then do a sample, then count out
full bit times and do samples in the center of the remaining bits.
I'm guessing that's the purpose of the counter, to get centered in a
bit to get a clean sample. Maybe I'm not understanding the encoding
scheme. Could you give an example of a waveform for a short bit
sequence?
-Dave