Re: never enough
From: "Jeff Fox" <fox@ultratechnology.com>
> Hi MISC readers,
>
> Wayne Morellini wrote:
<snip>
> > But I have oftened toyed with the idea of hooking a 32 bit misc up to
one of
> > the portable Graphic/3D processor with on chip memory (upto 32 MB on
chip
> > now, I think). Would certainly give enough memory for the program and
the
> > graphics. How possible would this be?
>
> It is completely possible, but not with programmable hardware as far as
> I can see. A memory bit requres 1+ transistor for DRAM and 4 to 6 for
> SRAM. 32MB is 256 mega bits, and that could be 1.5 billion transistors!
> There are no FPGA with 1.5 billion gates. If a million gate FPGA costs
> $10K would a billion gate FPGA cost $10M?
Excuse me... wasn't he suggesting taking an available graphics chip and
connecting that to a MISC chip using the video memory as system memory?
Would have some problems though, latency would be horrible and I think most
grahpics chips flush their pipeline before granting direct memory access.
<snip>
> The idea of the F21 design is to get a few hundred mips per megaword
> of memory or per 32K words or memory depending on the configuration
> of nodes.
What would the die size ratio (more meaningfull than transistor/gate #'s)
between memory and logic be in those cases? (assuming embedded DRAM)
> We are currently (in one project) looking at reducing the design by
> making I/O register based (no mems) and integrating a small amount
> of memory on chip and multiple nodes connected together on a chip.
> With wafer scale integration it looks like the upper limit is
> somewhere around 15 million Forth mips from a "chip" in production
> silicon today. Of course I personally don't have the money to
> do the design so "feasability" depends entirely on finding
> the money like most other things.
It has been clear for a while now that this kind of architecture is going to
play a big part, the popularity of the FPGA is a sign on the wall...
reconfigurability is a must, but FPGA's are too fine grained for a lot of
applications. Pixelfusion already has a chip capable of multiple tera-ops
for instance using the logic in memory approach (they use upwards of 1500
basic processing elements). They are more aimed at numerical processing
though, it was original meant to be a 3D processor... but they are now
trying to retarget it to networking applications. A MISC processor would be
better suited to the bit juggling required for that I think.
> One of the teams interested in the MISC multiprocessors are interested in
> compression/decompression and have the best software out there at the
moment.
Should I take "out there" and "best" with a pinch of salt? :) (the first
because you seem to enjoy being flamboyant about knowing secrets, and the
second because the story of supposedly revolutionary compression method's of
which the details or even results cant be divulged is so common a pitch) Or
are there any public references you could share?
Strange, you would assume video codec's would be more suited to processors
wich are better at numerical processing (for transformations and warping
motion compensation and the like) although I know theres at least one group
which uses adaptions of more conventional compression algorithms for state
of the art video compression using for instance Lempel-Ziv which I think is
more suited to MISC... so there might be more
(http://pier.ecn.purdue.edu/~dxm/Video/Overview/).
Marco
