Recent dialog and old initiatives

["Myron Plichota" <myron.plichota@xxxxxxxxxxxx>]

Dear readers:

It's good to hear the wires lit up again on this list! The tradeoffs between
different approaches to building a real live Forth chip have been
intelligently summarized lately, and the point was also acknowledged that
there are many ways to skin a cat. My own experiments in MISC design have
often been influenced by ideas posted on this list or published elsewhere,
notably the labors of love of Jeff Fox and David Cary.

Jeff's report on Dr. Ting's ideas for P24 was especially interesting to me
due to the (new to me) notion of an A-register stack. This is a great
example of clearing a commonly-encountered bottleneck by subtly changing the
rules without a ruinous impact to design economy. The evolution of the
instruction sets in the x21 chips has demonstrated a progression from bare
bones to bare bones with a few grudging nice-to-haves thrown in. I have had
a lot of fun experimenting with machine Forth on Jeff's MuP21 simulator and
homebrew F21+ instruction emulations in 32 bits on x86. I can see how the
presence of an A-register stack could affect programming style as
fundamentally as the original single A-register does.

If I were made of money, I'd produce a 64-bit x21-like MISC with a
full-lookahead carry adder, one or two additional instructions to augment
DSP capabilities, six or more serial links, and a glueless SDRAM interface
as the toppers in the features list. Putting a stake in the ground at 64
bits may seem excessive and arbitrary, but it banishes integer queasiness in
DSP algorithms and makes problems like pixel boffing and astrogation math
within better reach. A 64-bit address is not so far fetched when you also
consider virtual reality as a potential application. Maybe (probably) we'll
always want more.

A while ago, I raised the notion of "The 2's-complement Cookbook". Since I
last posted, I have implemented the CORDIC sin/cos algorithm in 32 bits on a
16-bit DOS Forth, an F21d+ emulation, and a direct-threaded code Forth on
TI's TMS320C6x DSP. I have also discovered some other interesting algorithms
and insights. If anyone is interested, some e-mail requesting copies would
spur me to organize things into a half-decent zipped attachment for general
consumption.

The Steamer16 CPLD design I posted a while back has been revamped to pack
five 3-bit instructions into each 16-bit cell, and HLL-support macros have
been implemented for the assembler. It's first application is a machine
vision system which will hopefully earn its keep in the real world of
CAD/CAM. Maybe I'll get an ROI on the minimum qty. of Cypress CY37128s I
broke my piggy bank to buy!

BTW, I strongly encourage anyone out there who wants to design their own
silicon to learn VHDL and use any one of the various low-cost tools
available. I have used 4 different vendors' tools so far, and they are all
_pretty good_. You can learn a lot and gain confidence from simulations even
if you never actually burn or otherwise fab a chip.

Myron Plichota