Re: never enough
From: "Nathaniel Downes" <down@ici.net>
> On Wed, 01 Nov 2000, Jeff Fox wrote:
<snip>
> > We are currently (in one project) looking at reducing the design by
> > making I/O register based (no mems) and integrating a small amount
> > of memory on chip and multiple nodes connected together on a chip.
> > With wafer scale integration it looks like the upper limit is
> > somewhere around 15 million Forth mips from a "chip" in production
> > silicon today. Of course I personally don't have the money to
> > do the design so "feasability" depends entirely on finding
> > the money like most other things.
>
> I got more than that.
How much of that can you fit into a single FPGA?
Also Im just wondering how you and Jeff handle the distribution of tasks
between all the different processing elements and the communication between
them. All under explicit software control? Or with a hardware scheduler
distributing tasks among them in some way?
Marco
