Re: FPGA's (was: Soft EEG)
- To: <MISC>
- Subject: Re: FPGA's (was: Soft EEG)
- From: <Eugene.Leitl@xxxxxxxxxxxxxxxxxxx>
- Date: Tue, 28 Nov 2000 17:26:28 +0100 (CET)
- Sender: eugene.leitl@xxxxxxxxxxxxxxx
Resent-Date: Mon, 27 Nov 2000 20:06:20 -0500
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From: Eric Laforest <ecl@pet.dhs.org>
To: wear-hard@haven.org
Subject: Re: FPGA's (was: Soft EEG)
Date: Mon, 27 Nov 2000 20:06:45 -0500
On Mon, Nov 27, 2000 at 02:52:26PM -0800, Doug Sutherland thus spake:
> mcarlson@inetnebr.com wrote:
>
> In theory one could implement
> the whole wearable on FPGA, but it's not really practical and
> would take a long time.
>
It would also be prohibitively expensive.
It would involve using a mid-to-high-end device like a
Xilinx Virtex300 or 1000, which is not cheap to begin with.
It would most likely end up requiring a multi-layer board.
Plus the Xilinx software for the faster chips costs more than the
average wearable and it's a *yearly* fee.
The Xilinx software is rather buggy too from what I hear from friends
who use it at work and from comp.arch.fpga.
I mention Xilinx in particular because most FPGA boards use their parts
and they happen to make the bigger and faster FPGAs out there.
> We don't need to do the whole wearable in FPGA but it does
> offer some serious possibilities in attacking the problems
> in video and audio inout/output (especially associated size
> and power consumption issues) and perhaps some interesting
> sensor device interfaces (biofeedback etc).
>
> -- Doug
Exactly. Like the Z80 idea, only more so.
The approach I want to use is to have several cheaper modules
(400$CAN or less) comprised of a small fast FPGA (ie: Atmel AT40K series)
it's config EEPROM, 64Kx16 of fast SRAM, some NVRAM/EEPROM/Flash for bootup,
a quad UART, and a simple bus to attach the data/addr lines of whatever device
you want to attach to the unit. This should fit on a small 2-layer
(top and bottom with thru-holes) board that can be custom-made cheaply.
(www.apcircuits.com)
This module acts as a native Forth CPU with the Forth compiler/interface
loaded into RAM (~8KB). One interfaces through the UART, through which
all commands and data flow. The CPU has also many IRQ and digital I/O
lines to control peripherals.
Each module controls a few devices and are interconnected together in
a simple pseudo-token-ring setup for example.
One or two talk to the user via twiddler, simple HMD/LCD, audio, etc...
The rest are are sensors/actuator and/or numbercrunchers/applications.
This would yield a system that is completely field-reprogrammable except
for the FPGA and the actual wiring. It can be as small or large as
needed. The entire HW and SW design can fit in a persons' head.
It can be homebrewed.
It would be COSHER. (except for the FPGA software)
The serial interconnections can be straight TTL, RS-232 or RS-422
(IIRC) depending on speed/distance and thus can be spread around the body
very easily. RS-232 is a very common interface, so that's a lot of
interoperability right there.
It would use less power than a typical wearable and have
more punch than a Z80 machine (or similar) in terms of processing
and of real-time behaviour.
It wouldn't do Linux, 800x600 displays or advanced speech-recog/synth
but it would be easily hackable both in SW and in HW.
Think of it as a set of small Apple IIs or C64s on steroids.
Anyway...enough ranting. Just my 0.03$ :)
Eric LaForest
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