[NOSC] Verilog Implementations

[krejasi JR <kallkorv@xxxxxxxx>]

Hi eric!

My attempt to do NOSC is by shematic and by CUPL when
i dont have acces to any VHDL tools wich by the way
are super huge and super expencive. Even the free
student versions from Altera and Xlinix are 
cumbersomly large.

But check out J Fox web pages with
links to various CPU designs.

BTW ,whats the mysterious problems?

KK

--- Eric Laforest <ecl@xxxxxxxxxxx> wrote: > Is there
anyone out there who is doing 0-operand CPU
> design in Verilog?
> I've seen several done in VHDL and a few done with
> schematics.
> 
> I'm currently attempting to do so, but am stumped by
> mysterious
> problems.
 
> Eric LaForest


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