[NOSC] Chuck Moore website and new Forth chips

[Mark Sandford <pagercam@xxxxxxxxx>]

--- Jeff Fox <fox@xxxxxxxxxxxxxxxxxxx> wrote:
> Mark Sandford wrote:
> > Agreed, but a chip (processor farm), that can't do
> a
> > significant/interesting demo, isn't much of a
> > technology demonstration. 
> 
> Can't?  I am currios why you say that.
> 
> But from what I have seen the demos that people want
> to see are ususally moronic and have nothing to do
> with what chips are good for.
> 
> Compression and decompression of data streams in
> realtime is pretty much an open ended problem,
> things like protein folding, gene sorting,
> simulations
> and problem modeling, AI, and a lot of other things
> that need computing power are not the sort of things
> the investors want to see.  They want to see a
> dancing baby doing the latest popular dance.  Then
> they don't pay for the demo and don't invest anyway.

Ok, let me rephrase.  Assuming the 25x is built what
problems do you see it solving and is this specific
configuration the best answer?  It appears to me that
Chuck put forth the 25x because thats what fits it 7
sq mm. which is the minimum size for MOSIS at 0.18,
thats fine, the next question is, is that the best
configuration or does code to be run need more than
384 "words", if it fits then this is the right answer,
if it doesn't you have the option of paging in code or
increasing memory size if the code is only a little
bigger, then increasing the on-chip is the right
answer.  If it is a lot bigger then more on-chip is in
feasible and paging will be required, it's fine either
way as long as you understand the trade-offs.  Some of
my concerns came with 25 processors feeding off a
single memory chip, if the processors are constantly
paging they don't get nearily the possible amount of
work done.  

As you correctly point out, most code is overly
bloated and inefficent and the HW industry has
accepted this bloat and then to L1, L2 and L3 caches
to overcome the poor programming.  You are also
correct in pointing out that small effiecnt code
requires significantly smaller bandwidth.  The
bandwidth requirements come in two parts, the program
(instruction) and data areas, effiecient coding
reduces instruction requirements but data is data and
can be reduced by effiecient design to some extent,
but generally this will not change much.  With the 25
processors and a single memory then, assuming each is
doing similar work they will have similar requirements
and thus get equal portions of the available
bandwidth.  If the extrenal memory is capable of 250
Mwords/Sec, then each processor could use no more than
10 Mwords/sec.  For some applications this is fine for
others this is not and the processors could be idle
much of the time.  For appliactions like AI, this
probably works out fine, for others the processors
starve.
 
-- stuff deleted

> > What is described above is the classic problem,
> and
> > one that has plagued the CPU industry for years. 
> This
> > has become a main mantra of mine, a system isn't
> > limited
> > nearly as much by MIPS as by memory bandwidth, and
> 
> Very true.  And by the programs being 100 times
> larger
> than they need to be.  The overhead is built into
> the
> systems to create the artificial problem that can
> be improved in little steps for marketing purposes.
> The easist problems to solve are these sorts of
> artificial problems, but they are what drives the
> industry.

Agreed

-- stuff deleted
> Instead of a single 1000Mhz processor with a huge
> cache (that is dwarfed by the size of the software
> overhead required) and a huge amount of memory, a
> design optimized to carry the markeing introduced
> overhead, the same number of transistors can
> be 1000x more efficient on problems that are
> parallel.
> 
> Almost all problems, certainly almost all
> interesting
> problems, are embarrasingling parallel.  The only
> problems that are not are the one we artificially
> created for ourselves in our antiquated serial
> computers with absurd computational overhead.
> 
> Humans don't look like Pentiums, they have 2*10^11
> processing nodes.  They don't run Unix or Windows.
> 

This is true, I have also had a fair portion of career
spent in parallel processing and the systems are
generally designed to be 1000 workstations rather than
10,000 efficent processors.  They have a full OS that
takes multiple megabytes to handle communications, a
big portion of which is getting "printf" statements
from this processor out to a control console.  I spent
a large portion of my career using the Inmos
Transputer, now defunct as it didn't fit peoples ideas
of what a processor should be but it followed many of
the MISC concepts.  Intrested parties should scoure
the web for information as it is a very powerful and
good model of what a minimalist processor should look
like.  It used byte codes and had a 3 element stack
architecture, it was designed to be programmed in a
high level languauge called OCCAM for which most
operations turned straight into byte codes so even
though it looked like a high level language (like C or
Pascal) it ran like assembly.  It also had 4
communications links that could tie to 4 other
processors and create a "computing surface".  It is
very low in transistor count and even contained a
process scheduler in hardware so that no OS was ever
required.  It fit with many if not all the MISC
concepts and the code was suffienctly small that n
many cases the processor could do many significant
functions completely from its 4Kbytes of on-chip
memory.  Many people missused it and added OS's and
large amounts of external ram but you could build very
powerfull systems efficently if you took simplicity as
a design goal.  There is much to be learned from this
processor and hopefully the 25x will use some of these
concepts.

> > 60,000 MIPS that can't be used is worthless, 
> 
> If it is considered useless it may never be made.
> If people keep repeating that it is useless other
> people will keep thinking it is useless.  If none
> are ever made the only value will be the educational
> value to the few people who study the good ideas
> that are there.
> 
> Some of the most brilliant people I have met love
> the idea of cheap chips with millions of mips.  But
> convincing people with money is a more difficult
> problem.  Convincing most people seems to simply
> be a matter of showing them that it has become
> mainstream.  They equate good idea with mainstream

I'm not trying to say that this is a bad idea, just
that bandwidth issues often dominate and limit
processing power so make sure that your processing
power has suffiecent bandwidth support, so it doesn't
spend all its time waiting for data.  Maybe my comment
are related to my current work which is developing a 
chip for voice processing that has 9 DSPs running at a
realitively high speed (10% of Chuck's 25x speed) and
we are bandwidth not MIPS limited so I put this
forward and caution that many people underestimate
thier bandwidth needs and get burned in the longrun. 
You can never have too many friends, money or
bandwidth.

Thanks - mark


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