Re: [colorforth] ILP of [colorforth]

["Samuel A. Falvo II" <kc5tja@xxxxxxxx>]

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I know this message was address to John M Drake, but...

On Tuesday 06 July 2004 05:16 am, Huibin Shi wrote:
> I am wondering if you once mentioned that FORTH processors use a
> simpler way to implement instruction level parallelism, though those
> processors do not use the superpipeline or superscalar stack
> architecture.

A single, simple Forth core really can't implement instruction level 
parallelism due to the inherently sequential nature of stack code.  
However, there are certain ways to cheat.

The first way is to bind multiple Forth cores to a single instruction 
pointer.  What you end up with here is a bizarre cross between VLIW and 
SMP.  For example, Bernd Paysan's 4Stack CPU does this.  A single 32-bit 
instruction word holds 4 8-bit stack CPU opcodes.  There are four 
distinctly different stack cores inside the CPU, each with its own data 
stack, though they all share the same return stack.

To fully exploit the 4stack architecture, one needs to perform "software 
pipelining," just as is done for common VLIW architectures today.  
Software pipelining is simply the process of deciding which core gets 
which instruction externally to the CPU (e.g., the compiler usually 
makes this decision).

Another approach to improving instruction throughput is to recognize 
certain combinations of stack words in aggregate.  Let's call these 
"phrases."  Phrases such as "SWAP DROP", "+ @", etc. can be recognized 
fairly easily by the instruction decoder, and treated as a single 
macro-instruction (e.g., SWAP DROP is NIP, and + @ is an indexed memory 
reference).  Assuming a relatively simple instruction set, implementing 
the logic necessary to make this happen is about as complex as 
modern-day CISC processors, and therefore, quite doable.  To the best of 
my knowledge, however, I'm not aware of any stack CPU that takes this 
approach, although Anton Ertl has brought the idea up a few times on the 
comp.lang.forth mailing list.

> Would you please advise where to find how FORTH processors realise ILP
> as superscalar stack processors?

I think Google or some other search engine is about as good as you're 
going to get.  The Forth hardware community is highly fragmented 
compared to even its software community.

- --
Samuel A. Falvo II
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