Re: [colorforth] ILP of [colorforth]

[John Drake <jmdrake_98@xxxxxxxxx>]

--- Huibin Shi <shi@xxxxxxxxxxxxx> wrote:
> Dear John M. Drake
> 
> I am wondering if you once mentioned that FORTH
> processors use a simpler way
> to implement instruction level parallelism, though
> those processors do not
> use the superpipeline or superscalar stack
> architecture.
> 
> Would you please advise where to find how FORTH
> processors realise ILP as
> superscalar stack processors?
> 
> Cheers,
> 
> Huibin

First off I'm not the "Forth chip" expert.  That
would be either Jeff Fox or Chuck Moore.  Hopefully
one of them will pipe in here.

Jeff Fox's site http://www.ultratechnology.com
explains this in great detail.  Specifically
look at:

http://www.ultratechnology.com/f21cpu.html#cpu

Basically Chuck Moore's designs since ShBoom 
all grab multiple instructions with one 
memory fetch.  ShBoom is a 32 bit processor 
with 8 bit instructions.  So it can grab 4 
instructions (32 divided by 8) with
each memory fetch.  MuP21 and F21 are 20 bit
chips with 5 bit instructions.  They can grab
4 instructions with one memory fetch 
(20 divided by 5).  

Note, this isn't "parallelism" in the sense
that more than one instruction is executed at
once.  But rather multiple instructions are
fetched at once.  This allows the processor
to be faster than memory access.  In can be
doing real work while waiting for the next
memory fetch.

I've crossposted this to NOSC (no instruction set 
computers) mailing list because it's really a
NOSC question.  Feel free to trim the follow
up to just the NOSC list.

Regards,

John M. Drake


		
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