F21 diagrams?
- To: MISC
- Subject: F21 diagrams?
- From: "G R A Dunbar" <G.R.A.Dunbar@xxxxxxxxxxxxxxxxxxxx>
- Date: Tue, 16 May 1995 12:47:12 GMT
- Organization: The Robert Gordon University
- Priority: normal
Can anyone point me in the right direction for internal block
diagrams of the F21?
I have been studying the F21 Prelim. Specs. posted here and I would
find a diagram helpful to explain the internal structure.
A "programmers model" showing the registers P, A, C, T, S(0..16) and
R(0..16) seems clear enough, but what other "transparent" registers
are there? Is there a memory address register (MAR) and memory data
register (MDR) to latch information to/from the external busses? Are
there any other transparent latches associated with the ALU? An
instruction decode register? Are there transparent stack pointers
associated with S and R? Am I right in assuming the data stack depth
of 18 is made up of T and a block of 17 S's and the return stack is
made up of a block of 17 R's?
I have made a diagram of the programmable registers and would like to
add the data paths. Is/are there internal bus(ses) or are the data
pathways point-to-point? (Primarily I am interested in the CPU and
not the coprocessors - for the time being at least.)
I have also tried to work out the Register Transfer operations for
the instruction set and have got stuck on some of them, in particular
1B, "over". On reflection my efforts have assumed textbook clocked
register CPU design, whereas I think I remember seeing somewhere that
the instructions are decoded and execute asynchronously as simple
combinatorial logic - is that true?
The F21 is a fascinating design. Any help welcome!
Regards,
Graeme
+-------------------------------------------------------------------+
| Graeme Dunbar |
| School of Electronic and Electrical Engineering |
| The Robert Gordon University |
| Schoolhill Tel. +44 1224 262415 |
| Aberdeen AB9 1FR Fax +44 1224 262444 |
| Scotland U.K. email g.r.a.dunbar@rgu.ac.uk |
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