Re: F21 diagrams?

[rdr@xxxxxxxxxxxxx (Raul Miller)]

G R A Dunbar:
   A "programmers model" showing the registers P, A, C, T, S(0..16)
   and R(0..16) seems clear enough, but what other "transparent"
   registers are there?

From my understanding, there's a latch/shift register that's used to
hold the instruction during instruction decode.

   Is there a memory address register (MAR) and memory data register
   (MDR) to latch information to/from the external busses?  

As I understand it, the A, R0 and P registers may each function as a
memory address register, and the T [and I] registers may function as
memory data registers.

   Are there any other transparent latches associated with the ALU?

As I understand it, the latch is T

   An instruction decode register?

I'm fairly sure there's an instruction register -- this would be
needed to properly sequence the four instructions contained in each
instruction word.

   Are there transparent stack pointers associated with S and R?  Am I
   right in assuming the data stack depth of 18 is made up of T and a
   block of 17 S's and the return stack is made up of a block of 17
   R's?

Close -- Basically, there's a 35 bit long (by 21 bit wide) shift
register.  Except it's discontiguous at the interface between R and T.
T refers to one particular location in this (set of) shift
register(s).  R refers to another.  Program logic drives the
shifting/latching action.

[Aside: the far end of the shift register is merely a latch -- when
stuff is dropped off the stack the bottom element is replicated.]

   I have made a diagram of the programmable registers and would like
   to add the data paths.  Is/are there internal bus(ses) or are the
   data pathways point-to-point? (Primarily I am interested in the CPU
   and not the coprocessors - for the time being at least.)

Best way to draw the data paths would be to analyze the instruction
set.  Anywhere you see a potential data flow you have a data path.

My [not very rigorous] impression is that S0, T, R0, and A are all
participants in a bus-like structure which includes the ALU.  Stepping
back a bit, I'd expect to see I, P and the external bus also
participating in this scheme.  Stepping back further, I'd expect to
see the other coprocessors hooked in -- focussing around the memory
coprocessor.

   I have also tried to work out the Register Transfer operations for
   the instruction set and have got stuck on some of them, in particular 
   1B, "over".  On reflection my efforts have assumed textbook clocked 
   register CPU design, whereas I think I remember seeing somewhere that 
   the instructions are decoded and execute asynchronously as simple 
   combinatorial logic - is that true?

True.

The F21 doesn't rely on latches for internal sequencing, instead it
uses "analog delay lines".  If you read the appendices in the MuP21
Programming Manual, you'll see that Chuck's OKAD package places a lot
of emphasis on capacitive effects.  You'll also see that main
processor speed varies with driving voltage (the video processor, on
the other hand, is clocked).

Raul Miller