Re: Unidentified subject!

[Eugen Leitl <ui22204@xxxxxxxxxxxxxxxxxxxxxxx>]

On Thu, 18 May 1995, Robert Hoeller wrote:

> 
> Dear Jeff,
> 
> here some comments on your F21 network specs:
> 
> >>>>> "Jeff" == Jeff Fox <jfox@netcom.com> writes:
> 
> ...
> 
>     Jeff> In normal operation the serial/network coprocessor will be
>     Jeff> reading and echoing serial data, but it will not be making
>     Jeff> any memory access.  
> 
> This is not exactly true. You are right, most of the serial port chips
> don't do any memory access. But nearly all network controller do some
> kind of memory access and most of them are able to do it via DMA!
> (see LANCE and friends)

I understood Jeff meant that once initiated, the action will
run without requiring further attention from the processor.

This is a good concept. While my router required caching of
each single message packet, this is not absolutely necessary.
Essentially, the routing code would just read in header
and process code, while the data stream would busily issue 
pad bytes, then decide which link to patch through.

The only thing I didn't quite understand: how many links are
there? Can one patch through through every link to every link?
Did you actually integrate a crossbar switch on the die?
Or does each transfer virtually block the processor?

Somewhat puzzled,

Eugene.
 
> ...
> 
> -----------------------------
> 
> You describe the network processor in some detail from the software
> point of view. But there is no information about the networking from
> the hardware-architectural point of view:
> 
> 	o	what kind of general concept (CSMA/CD <-> token ring <-> ???)
> 	o	what kind of collision detect / arbitration
> 	o	what kind of transmission medium
> 	o	what max. line length (derived from the points above)
> 
> 
> Robert
> 
>