P21i/o

[jfox@xxxxxxxxxx (Jeff Fox)]

Dear MISC readers:

> Andew asked:
>I don't understand; if you look at the state of the system in the
>middle of a write operation, the WE line is low and both the MuP21
>and 74245 are trying to drive the data bus.  I don't see how that
>can work.

Well you must remember that things don't happen instantly.  In the
case of a data access to slow ROM or RAM spaces (Dr. Ting's boards
map i/o into slow or fast RAM space) MuP21 takes about 25ns setting
up address and i/o lines then waits a long time for 250ns memory. 
This is so long when compared to the select pulse that you can latch
on either side of the pulse and as long as the timing of the chips
gets the data on the bus at the right time things are ok.

I didn't use a 138, I just just used some nor and or gates.
My circuit seemed logical while Dr. Ting's looks a little funny
because he used a chip that selects when a line goes from 0 to 5v.
This happens close enough to when the line goes to 0 that the
timing is ok.

>I guess my question is, can I just construct a system exactly as the
>schematic on page 92 shows with NO modifications and have a working
>system?  Once I accomplish that, I can test most of my questions myself
>instead of dumping them all on this mailing list.

Sure.  I didn't get a schematic, and as there may be different versions
I don't know what you are looking at exactly.  But the schematics I
have from Moore on Forth Engines are correct for that board.

>Is the '245 used for input and output, or merely for input?  If it's
>just input, it seems it'd make more sense to simply use a tri-state
>buffer instead of the '245 and have the WE pin ANDed with the output
>of the '138 to drive the buffer's Output Enable pin.  No need for a
>latching, bidirectional buffer when all you need is a nonlatching,
>unidirectional buffer.

If my memory of Dr. Ting's board is right then input.
There are three chips the 138 select either the input or
the output latch.  The output remains latched until it is reset
when selected by the 138.  The way the address and data lines are
connected to the 138 (or any other logic) determines the i/o addresses
that will map to external hardware i/o ports.

Jeff