Re: P21 Boot, Yet More

[Christophe Lavarenne <Christophe.Lavarenne@xxxxxxxx>]

   Date: Fri, 11 Apr 97 12:43:01 CDT
   From: lowry@htc.honeywell.com (Dave Lowry)

   Thanks, Christophe, for the explanation.  I suspected that the first word
   loaded was the "+ -until".  However, this seems like an odd choice.
   Why not build it into the DRAM like the rest of the bootloader?
   Or, since the instructions after the call to word' are not necessary the
   first time through, why not load those the way "+ -until" was loaded?

Remember the bootloader loop, it is made of four 20bits words:
   ( begin ) push call word'
   pop # nop nop
   ( 80 )
   ( MISSING: + -until )

Each loop iteration calls only once "word'" which loads 1 DRAM word from 3 ROM
bytes, so the first time around the loop, the 4th loop word "+ -until" may be
loaded (by "word'") before it's itself executed.
Why load more code from the 8bits mode bootloader?  Compared with 20bits mode,
it's slower and it's harder to build loops, because jump target addresses are
very limited (more on that point hereunder) and because literals, for addresses
and loop counters, are harder to build from code literals because only 8bits
literals can be read from ROM and their 12 high bits are scattered with address
bits.

   The call and jump instructions in 8 bit mode seem to use the entire 8 bits
   as the address argument, including the bit(s) used to specify the opcode.
   Then these 8 bits are inverted? aaaaa xored? to form the destination
   address?

On the P21, the call and jump instructions have the same effect whatever the
slot (1 to 4) or the mode (8bits or 20bits) they are executed from: they
override the 10 low bits of P (the program counter) with the inverted 10 low
bits of I (slots 3 and 4 of the instruction register).
Then in 8bits mode, as each read returns a 20bits word with the 8 low bits read
from the ROM and the 12 high bits from the address bus (which is shared with
the data bus), the call or jump opcode is executed from slot 3, so it's part of
the target address, so there are 8 different target addresses for each opcode
call, jump, jumpC=0, jumpT=0.
Because the 10 low bits of I are inverted to form the target address, the P21
assembler xors it with 155 (which is "2AA 3FF XOR").  I personnally found it
simpler to write my assembler with the bit scrambling ("AAAAA XOR") on
addresses and data reported at ROM-dowload time, so that all the rest of the
assembler (and the simulator) handles "regular" addresses, numbers, and masks,
so target addresses are XORed with 3FF when generating call/jump instructions.

CL