F21c

[jfox@xxxxxxxx (Jeff Fox)]

Dear MISC readers:

I said I would post some details about the F21c prototoype here.
ok, lets see.

F21c at this point is considered a prototype chip.  I expect we will
need at least one more prototype before production.

Power:
F21b had 3 power and 3 ground, F21c has 6 power and 6 ground. Hopefully
it is more than we need. If it then some pins may be freed up on F21d.
Video:
On F21b Vi Video in was not connected.  On F21c there is no Vi pin.
The Vo Video out (composite) is also missing on F21c.  F21c has
only RGB from the video coprocessor.  You will need an RGB monitor
with the built in video output.
Parallel Port:
On F21b there were 8 bits of data register, 8 bits of direction register,
and 8 pins.  On F21c some of the other i/o pins Ni,No,A10,A11,A12,A13 are
also mapped in the parallel port data and direction registers.  So if
these pins are not being used as Network or expanded SRAM addressing
they provide up to 14 bits of parallel i/o. (Ni/P8,No/P9,A/P10,A/P11
A/P12,A/P13) Also direction bits 18,19 control if P0 and P1 have
pull up or pull down.  P0 and P1 will have reduced drive on F21c
at 1/2 and 1/3 the power of the other Parallel Port pins.
Network:
Ni and No are now tri-state i/o because they are mapped on the parallel
port.  This allows multiple No to be connected to one Ni for network
topologies other than a ring to be constructed with no external hardware.
Analog:
no change.
New circuits:
a Real Time Clock register may be read or set.  It is incremented once
on each cycle of the Ci Clock in pin.  With a 20M Ci the 21 bit register
will overflow twice per second and a routine in a video interrupt or
other location will be needed to higher words of a clock count.
an experimental Echo Timing circuit on A/P13 can send out a pulse
and measure the time of the echo from the ground bounce on the line.
It latches the status of a series of inverters and provides an
accuracy down to .1ns.
Memory:
MuP21 provided only A0-A9 for SRAM addressing and thus supports 
only 1K of SRAM space.  F21a and F21b had A10-A12 pins to provide 
decoding for 8K words of SRAM.  F21c adds P/A13 which matches more
closely the 14bit page and 14bit homepage branch instructions in
F21 and provides decoding for 16K words of SRAM.  32Kx8 SRAMs
are about as cheap as 8Kx8 SRAMs now.
F21c contains 32 words of ROM on chip.  12 of the words in ROM are
mapped into 1K of ROM address space and my thus be used as unrolled
inner loops.  In F21c the ROM code will be some high level Forth
primitive words, a block move, a fill, and a multiply.  The jump
address into the code tables will determine the number of words
to be filled or moved. With 12ns access this code will execute
faster than code in DRAM or SRAM and will not generate an Offpage
status in the DRAM controller. 
this address space also provides a test clocking the cpu at 333mips
for the first time as compared to 200 and 100 in SRAM and DRAM.

Please understand that all numbers are preliminary.  If you ask
"exactly what is the power, or drive, or timing?" I can no more answer
that than I can the question "What bugs will you find in the design?"

Peter Jakacki wrote:
>I am offering a suggestion for the on-chip ROM on the F21 to allow
>booting a system without an external EPROM.

The original F21 spec allowed F21 to boot from the network.  This
means that no matter how many F21 you have you only need one to
boot of ROM (FLASH/NVSRAM/EPROM).  We may get that feature back
before production.  If not it adds a ROM to each node in the design.

>32K byte serial EEPROMs are available that require only 2 I/O lines
>clk+data) to be accessed. 
>
>Could the boot ROM include routines to read user code from here into
>RAM for execution. Also, some method would be needed to download via
>a serial port directly into RAM or the serial EEPROM.
>
>Actually, this is not really a question, more of a plea.
>
>I'd be more than happy to implement the code necessary once I get some
>idea of the size of the on-chip ROM available. I guess that the code
>would only require a few hundred bytes, although 1K would be more
>reasonable to allow for improved serial drivers etc.

Without on chip support the code needed to bit bang on the parallel
port would not likely fit in the ROM.  (see above)

>I've used this method before for OTP style micros with external RAM and
>it's still ok to use with an external EPROM just so that user code can
>be made non-volatile and still changed easily.

FLASH or NVSRAM is only a little more expensive than EPROM.  I like
PCMCIA.SRAM as a convienient NVSRAM.

It also sounds like a waste of the highest speed part of the chip to
do the slowest thing that it would do.

It sounds like it would be a good feature for a P8 type chip, but
Chuck has lost interest in working on that type of chip at the moment.
But he might like the idea of a P6 or P8 with + - Mclk Mdata . . . .
with i/o lines of some kind.  But of course it would require more
on chip memory to be useful.


Jeff Fox 
jfox@dnai.com    Ultra Technology Inc. 
http://www.dnai.com/~jfox/