Re: F21c

[Peter Jakacki <cybert@xxxxxxxxx>]

Jeff Fox wrote:
> New circuits:
> a Real Time Clock register may be read or set.  It is incremented once
> on each cycle of the Ci Clock in pin.  With a 20M Ci the 21 bit > register
> will overflow twice per second and a routine in a video interrupt or
> other location will be needed to higher words of a clock count.
> an experimental Echo Timing circuit on A/P13 can send out a pulse
> and measure the time of the echo from the ground bounce on the line.
> It latches the status of a series of inverters and provides an
> accuracy down to .1ns.

The timer circuit which interrupts the CPU at programmed intervals is
the basic building block of embedded systems, it is good to see F21
with this timer.

Chuck's echo timer put a smile on my face, at first I thought 'echo
timer, what can I use this for?', but when I saw the keyboard idea I
chalked up another one for Chuckie, good onya Chuck!

> Memory:
> MuP21 provided only A0-A9 for SRAM addressing and thus supports
> only 1K of SRAM space.  F21a and F21b had A10-A12 pins to provide
> decoding for 8K words of SRAM.  F21c adds P/A13 which matches more
> closely the 14bit page and 14bit homepage branch instructions in
> F21 and provides decoding for 16K words of SRAM.  32Kx8 SRAMs
> are about as cheap as 8Kx8 SRAMs now.

128K byte low-power 70ns SRAMs are readily available for around 
$7 (AUD), and high speed (10 - 25ns) devices are also available for a
little more. If F21 could address more SRAM then it could also run
faster, which is what we want, isn't it?

> The original F21 spec allowed F21 to boot from the network.  This
> means that no matter how many F21 you have you only need one to
> boot of ROM (FLASH/NVSRAM/EPROM).  We may get that feature back
> before production.  If not it adds a ROM to each node in the design.

If a network book is available, would it be possible to boot load F21
at a slower speed via an 8-pin PIC12C509 ($1) teamed up with a serial
EEPROM. The PIC chip normally would act as a system supervisor and
would control the F21's reset line, with an input into the PIC acting
as the watchdog strobe. At boot time the PIC reads the serial EEPROM
and bit-bashes this data into the network input so that the F21 can
boot from the code that is stored in the EEPROM.
 
> FLASH or NVSRAM is only a little more expensive than EPROM.  I like
> PCMCIA.SRAM as a convienient NVSRAM.
> It also sounds like a waste of the highest speed part of the chip to
> do the slowest thing that it would do.

I'd say that PCMCIA SRAM is expensive whereas a 64K byte 100ns EPROM
I can pick up for around $3 to $4. The idea of using an external EPROM
and a serial EEPROM is simply for booting purposes. Once the boot ROM
has loaded into RAM, the user code stored in serial EEPROM can also be
loaded in, ONCE. 

The cost of these serial EEPROMs is around the $2 to $3 mark and they
come in 8 pin DIP or SOL packs and they are cascadable. If it were 
possible to read the EEPROM from 32 words (I didn't realize it was that
small!), then it would be very convenient to be able to boot up a F21
from a cheap, non-volatile, space saving 8-pin device.

By the way, I'm surprised that a PLCC package is still being used as
it seems that with the high speed of the device a quad flat pack would
be used. I used to worry about soldering flat packs versus being able to
plug the PLCC part in, but when you consider the space that is saved,
plus the improved noise handling of the QFP, plus they are a lot cheaper
than their PLCC cousins, doesn't it make sense?

The QFPs are really quite easy to solder, especially anything with a
100 pins or less. It takes about 3 minutes to do this with a normal
soldering iron using a 'blob and reflow' technique.

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