Re: oversampling
- To: Bill Powell <whpowell@xxxxxxx>
- Subject: Re: oversampling
- From: KC5TJA <kc5tja@xxxxxxxxxxxxxxxxxxxxxx>
- Date: Tue, 6 Jan 1998 09:33:28 -0800 (PST)
- cc: MISC
- In-Reply-To: <6fdsKEAtgis0EwuT@mrv5.demon.co.uk>
On Tue, 6 Jan 1998, W H Powell wrote:
> They are also known as Sigma-Delta coders or Pulse Density
> Modulators. There are plenty of references - but few good explanations.
These are the devices that I'm most familiar with. :) The units that
Penio was describing (which also kinda makes sense -- just need to sleep
on it) works in a different way, but the end results are ultimately the
same.
> Look at it from the point of view of the D/A first. The best D/A is
> a real low-pass filter made with capacitors and inductors (those things
> wound with wire).
Yes, I know what an inductor is... :D For a really cheap unit, couldn't
you use a resistor though, forming an RC lowpass filter?
> rate 50 fold or more, otherwise the pattern you need to establish that
> level will have a low frequency component and get through the filter.
So if I have a signal, whose sampling frequency is 10kHz, and I want 8-bit
resolution, I will be needing to output the bitstream to the D/A converter
at a rate of 2560kHz, correct?
How much noise can I expect with a 2.56MHz bit output rate?
> But the filter can be very simple. This reduces cost. The anti-
> aliasing filter for a normal D/A has to cut off very sharply and this
> makes it an expensive analogue building block.
Interesting...
> Well not quite so easy. The feedback loop contains a filter, a
> binary comparator and a temporal sampler. Now you need a control loop
> expert to both make it 'stable' and make the error at the input to the
> comparator as small as possible to get a low error in that stream of
> bits.
So it's a phase locked loop, with the output of the VFO as your 1-bit
stream of converted data.
> And a control loop with an 'infinite gain element' (the comparator)
> with time non-linearity (the clock sampler) and a low-pass filter is
> physically simple and fairly easy to simulate but pretty intractable
74HCT9046A can operate at 16MHz... :)
> You can change a 1 bit A/D (with only two levels) to an 8 bit A/D
> with 256 levels by some digital magic called decimation. You have no
> problem getting equally spaced levels this way. In the process the
> sampling rate is greatly reduced - for example from 4 MHz to 8 kHz for a
> 64 kbit/s voice codec.
Please describe the probess of decimation. Is this basically how a flash
A/D converter works?
> The noise of a 1 bit D/A is frequency dependent. It is much better
> than other types as you go down to very low frequencies. The noise
> rises as you approach the cut-off of the low-pass filter.
This is true of any A/D or D/A system, though. Except with the multi-bit
units, they call that 'aliasing' errors.
> So how about DSP. Well all DSP I know of use 8, 12, 16, 24 or 32
> bit or even floating point words. You need ONE bit words at maybe 100
> times the speed. Maybe a DSP chip is useful. But the decimator is
Well, if we run, say, a 65816 system at a 16-MHz clock rate, we can
achieve, using DMA, a maximum sustained bit rate of 256Mbps, which is 100
times that guestimated for my example above. That should be perfectly
suitable for audio at a minimum (assuming my understanding is correct).
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