Re: oversampling
On Tue, 6 Jan 1998, KC5TJA <kc5tja@topaz.axisinternet.com> wrote
>On Tue, 6 Jan 1998, W H Powell wrote:
>
>> They are also known as Sigma-Delta coders or Pulse Density
>> Modulators. There are plenty of references - but few good explanations.
>
>These are the devices that I'm most familiar with. :) The units that
>Penio was describing (which also kinda makes sense -- just need to sleep
>on it) works in a different way, but the end results are ultimately the
>same.
Penio seems to be looking at the problem from the way the brain works.
It seems to have some interesting 1 bit functionality - but it outside
my competence to comment on that.
>
>> Look at it from the point of view of the D/A first. The best D/A is
>> a real low-pass filter made with capacitors and inductors (those things
>> wound with wire).
>
>Yes, I know what an inductor is... :D For a really cheap unit, couldn't
>you use a resistor though, forming an RC lowpass filter?
Yes. A sharper cut-off L/C filter may be useful in getting rid of out-
of-band noise more quickly though.
>
>> rate 50 fold or more, otherwise the pattern you need to establish that
>> level will have a low frequency component and get through the filter.
>
>So if I have a signal, whose sampling frequency is 10kHz, and I want 8-bit
>resolution, I will be needing to output the bitstream to the D/A converter
>at a rate of 2560kHz, correct?
I think so. I usually estimate A/D performance at a particular bit
rate.
>
>How much noise can I expect with a 2.56MHz bit output rate?
>
>> But the filter can be very simple. This reduces cost. The anti-
>> aliasing filter for a normal D/A has to cut off very sharply and this
>> makes it an expensive analogue building block.
>
>Interesting...
>
>> Well not quite so easy. The feedback loop contains a filter, a
>> binary comparator and a temporal sampler. Now you need a control loop
>> expert to both make it 'stable' and make the error at the input to the
>> comparator as small as possible to get a low error in that stream of
>> bits.
>
>So it's a phase locked loop, with the output of the VFO as your 1-bit
>stream of converted data.
Sort of! If you think of the rate of 'marks' as the frequency then you
could think of the frequency (of marks) indicating the encoded level.
>
>> And a control loop with an 'infinite gain element' (the comparator)
>> with time non-linearity (the clock sampler) and a low-pass filter is
>> physically simple and fairly easy to simulate but pretty intractable
>
>74HCT9046A can operate at 16MHz... :)
I found that a special comparator is not needed. Just use a 'D' flip-
flop. You can put a linear amp ahead of it to get more loop gain and
therefore a smaller 'error' between the input signal and the encoded 1
bit data.
>
>> You can change a 1 bit A/D (with only two levels) to an 8 bit A/D
>> with 256 levels by some digital magic called decimation. You have no
>> problem getting equally spaced levels this way. In the process the
>> sampling rate is greatly reduced - for example from 4 MHz to 8 kHz for a
>> 64 kbit/s voice codec.
>
>Please describe the probess of decimation.
This wasn't my job in the team. But I believe it is a FIR digital
filter.
The team designed it in two sections using a high speed technology for
the first section. This section was fast but simple because its input
was only 2 level. I think it did little more than add adjacent bits in
a shift register using a binary adder. One needs these 2 bit word
answers at only half the input rate. I think you can repeat this
procedure to go from 2 to 4 bit words, etc. and decrease the word rate
further. You can also do other than simple adding and use Hamming,
Hanning, etc over a longer string of bits.
> Is this basically how a flash
>A/D converter works?
No. I think a flash converter works more like a string of resistors to
set levels that are compared to the input in an array of comparators.
Flash converters are fast because they don't oversample, or count. But
I don't think they are accurate for more than words of 5 or 6 bits. A
one bit A/D plus a digital decimation filter can be extremely accurate.
>
>> The noise of a 1 bit D/A is frequency dependent. It is much better
>> than other types as you go down to very low frequencies. The noise
>> rises as you approach the cut-off of the low-pass filter.
>
>This is true of any A/D or D/A system, though. Except with the multi-bit
>units, they call that 'aliasing' errors.
I understand Aliasing to be folding of excessively high frequency input
energy into the pass-band. It can be folded anywhere into the passband
of the A/D.
This is different from the noise of 1 bit A/D which arises because it
cannot always make patterns having spectra that fall entirely outside
the pass-band.
>
>> So how about DSP. Well all DSP I know of use 8, 12, 16, 24 or 32
>> bit or even floating point words. You need ONE bit words at maybe 100
>> times the speed. Maybe a DSP chip is useful. But the decimator is
>
>Well, if we run, say, a 65816 system at a 16-MHz clock rate, we can
>achieve, using DMA, a maximum sustained bit rate of 256Mbps, which is 100
>times that guestimated for my example above. That should be perfectly
>suitable for audio at a minimum (assuming my understanding is correct).
More than enough I'd guess.
First assume that there is no feedback mechanism...
I look at a space as -1 and a mark as +1 level. These can be thought of
having random polarity as a starting point.
The absolute value of the output is therefore always '1'. And the
spectrum is 'white' noise (until rolled off at high frequencies by a
sinc function due to the pulse width i.e. clock period) We know the
power and spectral shape and therefore spectral density of this noise.
Our filter doing the D/A function takes only a fraction of this noise
because it has much narrower bandwidth than the one bit sampling clock.
So the noise will decrease at 3 db/octave with increase in clock rate.
But we use the feedback loop to modify the randomness of the bit stream
and try to match it to the input signal. If we use a first order filter
in the feedback loop the the noise improves at 6 dB/octave of clock
speed. If you use a second order filter in the loop it improves at 12
dB/octave. If you try to go to higher order you get a conditionally
stable system. (I have seen such a design for audio use)
So we can expect either 3 + 6 = 9 dB/octave (1st order) or 3 + 12 = 15
dB/octave (2nd order) rate of improvement with clock speed.
I made a number of empirical tests as well as doing some theory and came
to the conclusion that the unity gain band-width of the feedback loop
cannot not be made wider than (Clock-Freq)/Pi. With this I could
predict how much noise I would get in a given design, which might be
use only 0.001 of the clock speed for the analogue signal bandwidth.
--
Bill Powell. ( MIME, UU )
Atherstone, Warks., CV9 3AR. | Tel: +44 1827-718 945
<whpowell@iee.org> | Fax: -714 884
