Re: F21d - Video, Mup21 instructions.

[George Herbert <gherbert@xxxxxxx>]

>Jeff, good news, that 0.35 micron process (or 0.18 Micron process) might 
>be good for a second edition of the chip.

One thing I have been wondering about is whether the full-custom
chip design environment is in the end a plus or minus from the
perspective of MISC chips development alone.  There are a lot of ASIC
vendors out there with gate-array and similar technologies that are a
little less area and speed efficient compared to full-custom, but who
have up and running 0.25u and 0.35u fabs you can get space for in
production runs relatively easily.  I like Lucent and LSI Logic's
offerings, but there are lots of alternatives out there.

>More graphic colours and sound would be good (but this is I21 type 
>matarial).  All we really need is preferably: video bus, memory bus, USB 
>(or Firewire bus for I/O) buss, and legacy parallel/serial/Analoge and 
>microwire (borad level electronics buss) ports.  Almost any thing could 
>then be plugged in.

Dare I ask... PCI?  People keep selling MISC short by aiming it
only at low end applications.  Think bit bigger.

>I think we however are getting beat on the memory side of things, a lot 
>of memories are being designed for sequential access as backups to cache 
>systems, solutions:
>
> small on chip cache
>- A snow flakes chance in ..

Actually, if you go to a gate-array ASIC process, they have big fast
SRAM blocks pre-laid out which you just have to graft into your chip.
You don't even necessarily have to change the memory architecture;
you could add them inline with the existing memory access, just as
a faster SRAM to run out of...

> in package memory die
>- A reduction in headache for Chuck designing memory modules and less 
>charging time on the pads.

MCM is an expensive technology, exactly opposite of cost reduced chips.

>On chip memory (or should I say on memory F21)
>-  I listed some alternatives of people with the facilities in last 
>message.  Benifits, very tight interface to memory.

There are several DRAM processes set up to do logic as well,
should you want to impliment a Berkeley IRAM type design.
Toshiba is the apparent obvious choice from having investegated
them in some detail.  IMHO, on chip DRAM or visa versa is not
solving the right problem... DRAM is largely latency not
bandwidth limiting, so you want to avoid DRAM hits as much
as possible, which means SRAM caches are more important
close by than DRAM is.


-george william herbert
gherbert@crl.com