Re: F21d - Video, Mup21 instructions.

["Wayne Morellini" <waynemm@xxxxxxxxxxx>]

Chuck, Jeff See new Chip debuging section below

>One thing I have been wondering about is whether the full-custom
>chip design environment is in the end a plus or minus from the
>perspective of MISC chips development alone.  There are a lot of ASIC
>vendors out there with gate-array and similar technologies that are a
>little less area and speed efficient compared to full-custom, but who

I think the cheapness, power and speed advantages are great (is there 
many 0.8 micron Gate arrays that allow 500Mhz?) I think the main problem 
is that the system of design rules is not worked out so design come up 
quickly and reliably.  I mean it has been years and still no I21/F21 the 
mup21 the 6 month wonder took just as long.  This probably requires a 
bunch of Engineers to put a bunch of experimental test circuits on chip 
runs and test which ones do and don't work, I would have hoped it would 
have been worked out by now.  Maybe a safe version (with the tiles 
spread a little) to start off production then refinement for proceeding 
generations, the x86 processors do it.  But I know what you mean, if we 
were using Gate Arrays we would have had product by now.

CHIP Debbugging
===============
I just remembered something that I was going to write before.  I had an 
article on a new cheap process for debuging chips that is right up Chuck 
alley.  The process had something to do with malfunctioning circuits 
producing UV light, so by looking at operating bare die in the UV 
spectrum you could see which circuits were working or not.  Now thuis 
would be much faster and easier than external tresting, also something 
like this could be "rigged up".  The chips are small well spaced and few 
components.

>
>Dare I ask... PCI?  People keep selling MISC short by aiming it
>only at low end applications.  Think bit bigger.

Yes for an ?32 (please drop all the other stuff and bring a 32 bit 
version) and external PCI bridge would be great, how much logic would an 
internal PCI support take?  If we incorporate video on chip then half 
the need for PCI dissapears, still an interface to the AGP Socket-X or 
the processor on a Socket-X chip would be great.  Unfortunately I can't 
even afford a socket-X chip at the moment.

>You don't even necessarily have to change the memory architecture;
>you could add them inline with the existing memory access, just as
>a faster SRAM to run out of...

Mmm yes.

>
>> in package memory die
>>- A reduction in headache for Chuck designing memory modules and less 
>>charging time on the pads.
>
>MCM is an expensive technology, exactly opposite of cost reduced chips.

But cheap board costs (well at least one 3-D stacking process had claims 
that resulted to that effect).

>as possible, which means SRAM caches are more important
>close by than DRAM is.

Does reducing the loading time on DRAM pads help the situation?
>
>
>-george william herbert
>gherbert@crl.com
>
>
Good effort George, I hope the higher Misc powers got some ideas.

Wayne.

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