MISC-ShBoom-MuP21-F21

[Tom Vermeiren <Tom.Vermeiren@xxxxxxxxx>]

Hello everyone,

I am new to this discussion-group, so I hope you don't want to shoot
me for asking stupid questions or such. I've tried to catch up with
taking a look at the archive, but there were still a couple of questions
that kept unanswered. By the way, I just signed up last night and I must
say that you guys are sending at a high rate.

I was happy to notice that you started talking about ShBoom. I'm not very
familiar with the concept, but I'm interested. I would like to know where
I can find the Instruction Set of that architecture, or rather the
PSC1000. I'm also curious about the link between the MISC founders and
those of ShBoom and if the PSC1000 can be considered as a bigger, more
commercial implementation of a couple of the ideas behind MISCs.

About the MuP21 now, is there a representation of the insides of the
processor available somewhere. I mean a scheme where the ALU, the
registers, stacks and so on all figure and is pointed out how they're
connected.

What are the timings for instructions on MuP21 and F21 in clockcycli?
Haven't found this yet, and it will probably just be one cycle, but what
about the memory instructions? And what if some memory instruction keep
the memory busy, so that there can't be fetched another 20-bit word?

And last, is there any progression made with the i21? I'm not sure what
the difference will be between the 3 (MuP, F and i).

Anyway, this was my first time. Have some mercy. I know that I'm asking a
lot and much, but I would greatly appreciate it if you could point at
least a few things out for me. Like I said, I've tried to gather as much
information from the www as I could, but there were still some blancs with
me. I'm also new to this research so...
Thanks in advance.

Greetings, Tom.

P.S. For the interested reader (the odd one that is left): I'm making a
study about odd, fresh or renewing architectures and concepts. That's why
I'm interested about the MISC, because it continues in the direction
pointed out by the RISC-concept where the big designers of RISC-processors 
made a turn to the CISC-side of things. Anyway, suggestions about what you
think are interesting processors, are always welcome. And those don't have
to come on this mailing list, as far as I'm concerned.