Re: MISC-ShBoom-MuP21-F21
Hi Tom,
best wishes and welcome to this list,
On Thu, 18 Mar 1999, Tom Vermeiren wrote:
> I was happy to notice that you started talking about ShBoom. I'm not very
> familiar with the concept, but I'm interested. I would like to know where
> I can find the Instruction Set of that architecture, or rather the
> PSC1000.
The best resource is www.ptsc.com, the internet address of Patriot
Scientific Inc. There you'll find a complete manual about the PSC1000 with
a discription of all coprocessors.
> I'm also curious about the link between the MISC founders and
> those of ShBoom and if the PSC1000 can be considered as a bigger, more
> commercial implementation of a couple of the ideas behind MISCs.
The MISC Model evolved over the years as Chuck minimized his own
invention: FORTH. The Sh-Boom was a step towards the later MISC-idea.
It is really sad that Chuck hasn't get the success he should have had with
his amazing design ideas and creative energy in chip-research. But as he
told himself he has made many mistakes.
1) He broke up with nearly any standard. With the FORTH standard, too.
2) His ideas of productive working and designing chip, his ideas about
superb software and software technics are refused by most people, even
in the FORTH community.
3) He has refined his methods in a way that people can't understand it
anymore and as he mentioned again himself it would be nearly impossible
for others to use his tools to do senseful things.
Patriot Scientific used the old patented Sh-Boom idea and put modern and
good peripherals around so that the product could be sold, is stable and
well documented. Sh-Boom was designed in gate-array design, but
frustrated with this approach Chuck started to explore the VLSI design.
Many ideas of the Sh-Boom went into the new processors, but consequently
minimized. Dr. C. H. Ting produced with Chuck the first so called MISC,
the MuP21 ( MUlti-microProcessor 21-bit ). Marketing of MuP21 ( P21 ) is
difficult, too. I like Dr. C. H. Tings way of having fun. I have adopted a
certain attitude towards the bare minimum where you have to do all things
on your own from the scratch. ( I mean at least the board and the
processor is there! So the most difficult part to awake the silicon to
life was solved by Chuck and Dr. C. H. Ting and Mr. Jeff Fox ... ) but
all the rest doesn't really exist if compared to industrial standards. You
have to invent the most part on your own. To give you an example: When the
LED on my board turned on, I was so happy and amazed. I didn't see
anything on the TV, I couldn't even communicate to the board, because I
first had to write the communication software. The next step then is to
understand the minmal metacompiler, the 8-bit boot-code and video driver
code to set up a more convenient OS and to burn it into another EPROM,
then replacing the old one and hoping that the board will boot etc. ...
and if luck isn't with you you can start again. I like this way of having
fun and working with the bare minimum and creating my own system because I
learn a lot and noone can take this away. But I think most people don't
understand it, my friends call me absolutely crazy. )
However, F21 is under development for more than eight years. It is Jeff's
low-fat computer. It seems that he has some working chips now, but they
still have to be fully debugged. Money is always a problem and so Jeff
has reached a period where further steps are seriously dangerous.
i21 is very similar to F21 as I know and it is produced and prepared for
marketing in TV set-top-boxes at iTVc, a company founded by Chuck and
others. They have found investors but because of a lack of information
noone really knows what's going on there. F21 is an improved and extended
version of MuP21 with memory, video, network and I/O-coprocessor
integrated, where P21 only has only the memory and video co-processor. F21
runs with a five times higher clockcycle and has 2 more CPU instruction
than P21. ( 25->27 )
You can find all published MISC- materials via Jeff's WEB-pages
www.ultratechnology.com.
> About the MuP21 now, is there a representation of the insides of the
> processor available somewhere. I mean a scheme where the ALU, the
> registers, stacks and so on all figure and is pointed out how they're
> connected.
I haven't found a design-plan, yet. But Chuck presented one at his
fireside chats about the development of P21 at the FIG-days.
> What are the timings for instructions on MuP21 and F21 in clockcycli?
> Haven't found this yet, and it will probably just be one cycle, but what
> about the memory instructions? And what if some memory instruction keep
> the memory busy, so that there can't be fetched another 20-bit word?
MuP21runs at about 100MHz and F21 at about 500MHz.
Every instruction executes in 10ns on MuP21 and 2ns on F21.
Memory access depends on different things. The memory coprocessor gives
the higher priorities to the coprocessors, to let them execute their
instructions in parallel but with memory access first. ( Important to
maintain correct timing for the video processor that has the highest rank
of all ). So the CPU has to wait. Further it depends on which kind of
memory you want to access and if the access is on-page or off-page. Memory
access time is something between 12 and 250ns.
An F21 example in SRAM ( 12ns )
dup dup -or com
2 +2 +2 +2 8ns instruction time + 12ns SRAM access
in parallel : 2 2 2 2 8ns memory setup time
The memory setup time begins when no other memory access is pending, so
the 8ns in this example start in parallel with the first 'dup' and are
done after the 'com' so that now only 12ns are needed to complete the
instruction fetch of the new word.
(LIT) # a! nop nop
2ns+8ns setup+12ns SRAM +2 +2 +2
in parallel 2 2 2 +2 8ns memory setup time
# fetches a literal from the next word, so it needs a complete memory
access. after the last nop there's another 2ns memory setup left for the
next instruction prefetch and the 12ns access time, so there are 14ns
needed after the last 'nop' to complete the instruction fetch.
( DRAM onpage 55ns, off-page 140ns ) on-page means the same 1KWord-block
of memory, off-page: a different 1KWord-block
The chips have their main working area from 00000 - FFFFF in DRAM,
the higher part 100000 - 1FFFFF is for SRAM, boot-ROM, I/O and
configuration.
As I've understand it so far, but please have a look at the WEB-pages,
you'll find all information in their.
> Anyway, this was my first time. Have some mercy. I know that I'm asking a
> lot and much, but I would greatly appreciate it if you could point at
> least a few things out for me. Like I said, I've tried to gather as much
> information from the www as I could, but there were still some blancs with
> me. I'm also new to this research so...
> Thanks in advance.
I have a lot of fun with this stuff ...
> P.S. For the interested reader (the odd one that is left): I'm making a
> study about odd, fresh or renewing architectures and concepts. That's why
> I'm interested about the MISC, because it continues in the direction
> pointed out by the RISC-concept where the big designers of RISC-processors
> made a turn to the CISC-side of things. Anyway, suggestions about what you
> think are interesting processors, are always welcome. And those don't have
> to come on this mailing list, as far as I'm concerned.
Very interesting!
Best wishes, I hope there's some material for you to work with,
Soeren <tiedema@mail.uni-freiburg.de>
