FPGA'able RISC CPU

[Jaap van Ganswijk <ganswijk@xxxxxxxxx>]

Hi all,

I think this is an interesting new RISC CPU design. Especially the
16 bits design, since it only has two instructions: ADD and NAND.
In this case the IP (instruction pointer) has to be one of the registers
of course.

>Date: Tue, 28 Mar 2000 13:13:49 +0200
>From: Stanisław Skowronek <design@thesis.cjb.net>
>To: ganswijk@xs4all.nl
>Subject: Look At This If You Have Time
>
>Jaap,
>
>Have a quick look at www.thesis.cjb.net. I hope it is interesting. (the
>16bit machine has been already _prototyped_ on QuickLogic FPGAs and
>works well with 50 MHz . Didn't ever check higher speeds since I don't
>have xtal oscs working faster at the moment :-)
>
>Stanislaw Skowronek (registered in ChipDir - great page!)

For your clicking convenience:
http://www.thesis.cjb.net/


Groeten/Greetings,
Jaap

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