Technical aspects of the f21

["David Cousins" <deah@xxxxxxxx>]

Ok. So you've all heard about the PowerVR2 chip, right? It's not related to
MISC at all; it's a graphics chip that employs 512 internal custom
processors they call pixel engines, to render video at a fast enough speed
to compare to modern designs. This got me thinking... (please correct me on
any mistakes)

The f21 had about 7000 transistors, with about 3000 comprising the core. The
data width was 20/21bits, and the chip has been tested to about 800MIPS at
1.0um design. Conceivably the chip could either run faster or more reliably
at higher density technologies (such as 0.35um or lower), to target a real
sustained 500MIPS, which is all I care about on this little excursion.

So you take 240 raw f21 cores (3000 transistors each), and 16 with the
video/audio/networking on chip (7000 transistors). Use DRAM on a chip
technology (1 transistor/bit) or SRAM (4 transistors/bit) to provide them
with a shared 64k of RAM, and 256bytes of unique RAM for each chip, for a
total of about 128k. The DRAM should be very very wide (1000's of bits wide)
to provide the data rate for the chips (similar to Sony's Emotion Engine at
2560 bits). Additionally, have access to external RAM, either through the
f21's normal address range, or a DMAC that shuttles data to and from the 64k
pool.

Estimated chip size: 3000x240 + 7000x16 + m x 65280 + m x 256x256
    962,816 transistors (DRAM)
    1,355,264 transistors (SRAM)

All the processors run the same code (though they do not have to be at the
same point in the code), aside from the 256bytes, which could be either for
some custom code or local data for each chip. At 500MHz ~ 500MIPS, this
puppy is now getting a mear 128BIPS. The PowerVR, I estimate, makes use of
about 76.8BIPS (from what I've been able to estimate) from it's 512 Pixel
Engines, just for comparisons sake.

Now if one were to write a 3D rendering program for these chips (since 3d is
highly reiterative and simple mathematically, and massively paralellizable),
could the rendering performance meet or exceed that of the current
generation of chips (such as the PowerVR2)? I personally believe it would,
though there's no evedence to support me, since no one has ever written a 3D
program in forth (not that I've been able to find anyway). 128BIPS is mind
numbing, even if the most complicated instruction is a shift...

What do you think?

    -- Dave