Technical aspects of the f21
David Cousins writes:
> total of about 128k. The DRAM should be very very wide (1000's of bits wide)
> to provide the data rate for the chips (similar to Sony's Emotion Engine at
> 2560 bits). Additionally, have access to external RAM, either through the
> f21's normal address range, or a DMAC that shuttles data to and from the 64k
> pool.
Instruction slot type stuff doesn't scale to ultra wide buses, I'd
recommend something like
http://www.lrz-muenchen.de/~ui22204/.html/txt/8uliw.txt
It's all moot, since no one of us has resources to prototype stuff
like this anyway. (20 M$ a single prototype batch, right?)
