F21 docs
- To: fox@xxxxxxxxxxxxxxxxxxx (Jeff Fox), misc
- Subject: F21 docs
- From: Mike Simon <msimon@xxxxxxx>
- Date: Mon, 05 Jun 2000 18:49:24 -0700
- In-Reply-To: <200006050442.VAA55505@value.net>
I have noted some complaints in this list about the F21 docs.
I think the criticism is unjustified. Let me tell you why:
F21 is a very simple but hard to understand processor.
The most complicating factor is the address incrementer.
Here is what I think happened. Chuck found that the simplest
fastest incrementer included an inversion with each pass. This makes the
addressing scheme hard to follow.
The instruction decoder is a little unusual but not terribly so.
Nowadays these hardware simplifications are easily dealt with in the compiler.
None the less it requires considerable thinking to 'get' it.
I have found the doc adequate to design this chip on a board including
software.
================================
What might make doing a chip on FPGA useful is having separate memory managers
for processor, video, audio, and serial comms. Pins are cheaper on FPGAs.
And 12ns Static RAM is low cost too.
A serious processor for machine control might run $600 to $800 in small
quantities.
Simon