[NOSC] Verilog Implementations

[krejasi JR <kallkorv@xxxxxxxx>]

> Is there a free/cheap schematic capture program for
> DOS/Win/Unix that can export to netlists or such so
>as to be suitable for  FPGA implementation?
> (and capable of simulation would be a plus)

Linux people are doing their stuff at:
http://www.linux.org/apps/all/Office/CAE.html 

> And what is CUPL?
Cornell University Programming Language. 

Links:
http://www.ee.washington.edu/class/371/doc/cupl.html
http://www.pionix.co.kr/ldi/cupl.htm

ASIC:
http://www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/ASICs.htm#anchor11320

Besides where can one find standard cell library?
Is it even available on the net??

> You can go see at 
> http://pet.dhs.org/~ecl/lswmfsc/

Hmm.
 
> This is 5 implementations of a push-down stack with
> waveform dumps
> After 10+ tries, I'm seriously thinking of dropping
> HDLs altogether
> and going back to schematics...besides, a good NOSC
> chip should
> be simple enough so as to be manageable as a
> schematic. :)

That is what i have found out too! :-)
Actually, wich development software beeing used for
the NOSC design, VERILOG,VHDL,CUPL or plain schematic
is "not" the problem i think. The problem i find is
to find a compiler/assembler, floor planner for the
binary design file!

> creating a VLSI layout and getting it fabbed at
> MOSIS
> (which tends to cost ~1000$US/mm^2 for a run of 0-25
> chips)
> would make more sense.

Ofcourse it would be more sense. Im quite shure that
J Fox has somthing to say about MOSIS and general
silicon hassle and stress! :-)

KK


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